Design and Performance Analysis of Hardware Accelerator for Deep Neural Network in Heterogeneous Platform
dc.contributor.advisor | Aslan, Semih | |
dc.contributor.advisor | Qasem, Apan | |
dc.contributor.author | Sefat, Md Syadus | |
dc.contributor.committeeMember | Asiabanpour, Bahram | |
dc.contributor.committeeMember | Valles, Damian | |
dc.date.accessioned | 2022-01-14T15:48:31Z | |
dc.date.available | 2022-01-14T15:48:31Z | |
dc.date.issued | 2018-08 | |
dc.description.abstract | This thesis describes a new flexible approach to implementing energy-efficient DNN accelerator on FPGAs. Our design leverages the Coherent Accelerator Processor Interface (CAPI) which provides a cache-coherent view of system memory to attached accelerators. Computational kernels are accelerated on a CAPI-supported Kintex FPGA board. Our implementation bypasses the need for device driver code and significantly reduces the communication and I/O transfer overhead. To improve the performance of the entire application, we propose a collaborative model of execution in which the control of the data flow within the accelerator is kept independent, freeing-up CPU cores to work on other parts of the application. For further performance enhancements, we propose a technique to exploit data locality in the cache, situated in the CAPI Power Service Layer (PSL). Finally, we develop a resource-conscious implementation for more efficient utilization of resources and improved scalability. Compared with the previous work, our architecture achieves both improved performance and better power efficiency. | |
dc.description.department | Engineering | |
dc.format | Text | |
dc.format.extent | 111 pages | |
dc.format.medium | 1 file (.pdf) | |
dc.identifier.citation | Sefat, M. D. S. (2018). Design and performance analysis of hardware accelerator for deep neural network in heterogeneous platform (Unpublished thesis). Texas State University, San Marcos, Texas. | |
dc.identifier.uri | https://hdl.handle.net/10877/15152 | |
dc.language.iso | en | |
dc.subject | hardware | |
dc.subject | accelerator | |
dc.subject | DNN | |
dc.subject | FPGA | |
dc.title | Design and Performance Analysis of Hardware Accelerator for Deep Neural Network in Heterogeneous Platform | |
dc.type | Thesis | |
thesis.degree.department | Engineering | |
thesis.degree.discipline | Engineering | |
thesis.degree.grantor | Texas State University | |
thesis.degree.level | Masters | |
thesis.degree.name | Master of Science |
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