Hardware Accelerator for Elias Gamma Code

Date

2017-08

Authors

Ranganathapura Chandrai G, Karuna

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Abstract

Elias Gamma code, developed by Peter Elias, is a universal lossless compression method applied to unbounded positive integers. Extensive research on this coding technique has led to the development of many derivatives. However, much of these studies focus on the software realization of the Elias Gamma code, with limited emphasis on the hardware implementation. This thesis presents three designs of Hardware Accelerators, which are analyzed and compared with respect to the efficiency metrics. Given that the compression ratio of Elias Gamma is predetermined, the efficiency metrics included are throughput, latency, and cost. The research derives these metrics by targeting the design to the Xilinx Zynq™ Field Programmable Gate Array (FPGA). Each model builds on the previous design, with the Fundamental design achieving a compression throughput of 4.63 M symbols/sec and a decompression throughput of 18.5 M symbols/sec. The optimized design delivers a maximum compression throughput of 23.8 M symbols/sec while maintaining a decompression throughput of 18.5 M symbols/sec. The maximum compressed throughput converts to 190.4 M bits/sec with each symbol equating to 8-bits, whereas the decompression throughput translates to 592 M bits/sec with symbol size of 32-bits. In comparison to a reference software implementation, the optimized design provides 72x compression speed-up and 37x decompression speed-up.

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Keywords

Hardware accelerator, Elias gamma, Compression, Decompression, Packing, Unpacking, FPGA, ASIC

Citation

Ranganathapura Chandrai G, K. (2017). <i>Hardware accelerator for Elias gamma code</i> (Unpublished thesis). Texas State University, San Marcos, Texas.

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